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completed phase 1?

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Jaka Furlan 2025-11-29 20:28:00 +01:00
parent 0332001ef8
commit bc78a83838
11 changed files with 306 additions and 44 deletions
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32
ass2/SICocaml/processor.ml
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@ -47,6 +47,12 @@ let writeMemAddr (state : state) (address : int) (value : int) : unit =
Bytes.set state.memory (address+1) byte2;
Bytes.set state.memory (address+2) byte3
(*popoč za pisanje instrukcij*)
let write_instruction3 (state : state) (address : int) (byte1 : char) (byte2 : char) (byte3 : char) : unit =
Bytes.set state.memory address byte1;
Bytes.set state.memory (address+1) byte2;
Bytes.set state.memory (address+2) byte3
(*povečaj pc za i*)
let pcIncrement (state : state) (i : int) : unit =
state.regs.pc <- state.regs.pc + i;
@ -78,4 +84,28 @@ let write_register_int (state : state) (reg_code : int) (value : int) : unit=
| 6 -> state.regs.f <- float_of_int value
| 8 -> state.regs.pc <- value
| 9 -> state.regs.sw <- value
| _ -> failwith "Invalid register code"
| _ -> failwith "Invalid register code"
let print_memory (state : state) (n : int) : unit =
let mem = state.memory in
let len = Bytes.length mem in
let limit = min n len in
Printf.printf "Memory dump (first %d bytes):\n" limit;
for i = 0 to limit - 1 do
let byte = Char.code (Bytes.get mem i) in
Printf.printf "%02X " byte;
if (i + 1) mod 16 = 0 then Printf.printf "\n";
done;
Printf.printf "\n"
let print_regs state : unit =
let regs = state.regs in
Printf.printf "A: %06X\n" regs.a;
Printf.printf "B: %06X\n" regs.b;
Printf.printf "X: %06X\n" regs.x;
Printf.printf "L: %06X\n" regs.l;
Printf.printf "S: %06X\n" regs.s;
Printf.printf "T: %06X\n" regs.t;
Printf.printf "PC: %06X\n" regs.pc;
Printf.printf "SW: %06X\n" regs.sw;
Printf.printf "\n"