From bc78a838382ff65da06aec0ffd4d48ea55fbe383 Mon Sep 17 00:00:00 2001 From: Jaka Furlan Date: Sat, 29 Nov 2025 20:28:00 +0100 Subject: [PATCH] completed phase 1? --- ass2/SICocaml/decoder.cmi | Bin 566 -> 566 bytes ass2/SICocaml/decoder.cmo | Bin 629 -> 629 bytes ass2/SICocaml/izvajalnik.cmi | Bin 3022 -> 3169 bytes ass2/SICocaml/izvajalnik.cmo | Bin 9812 -> 11085 bytes ass2/SICocaml/izvajalnik.ml | 116 +++++++++++++++---------- ass2/SICocaml/izvajalnikF4.ml | 155 ++++++++++++++++++++++++++++++++++ ass2/SICocaml/opcodeTable.cmi | Bin 3154 -> 3251 bytes ass2/SICocaml/opcodeTable.cmo | Bin 5257 -> 5466 bytes ass2/SICocaml/opcodeTable.ml | 4 + ass2/SICocaml/processor.ml | 32 ++++++- ass2/SICocaml/test.ml | 43 ++++++++++ 11 files changed, 306 insertions(+), 44 deletions(-) create mode 100644 ass2/SICocaml/izvajalnikF4.ml create mode 100644 ass2/SICocaml/test.ml diff --git a/ass2/SICocaml/decoder.cmi b/ass2/SICocaml/decoder.cmi index 86f3866dd4609689af632777e9300bf7888678cc..455628f9ceaaff1ded27cb45957b6abaf357fcd7 100644 GIT binary patch delta 28 kcmdnSvW;cK14aSqxxP!Yo_qX#FQp@ycH#TW$sZWq0JrcBga7~l delta 28 kcmdnSvW;cK14e-(Hka>cJTeV!ezo1?{N@_2$sZWq0K$k3g8%>k diff --git a/ass2/SICocaml/decoder.cmo b/ass2/SICocaml/decoder.cmo index df363d3511db94948cec6bc9ac1bdacbb9b8eadb..23b814fd0eaee2fe84bd6993609b3730fc010bc2 100644 GIT binary patch delta 28 kcmey$@|9(SFq44vT;HWx&prOWm(r0;yYT(xWM!rx0I-Y|z{)O9c_~-kLJTh4y|Q>;-g{9bUya%L zC|i|g8XwIvRyJCVrD!V3N^pVs@ZNdHZm_I zk*)$NB3+s1v~J&Tl$m~Mj%hLzoaUHGtV5HDwGI_4)24+=MLDP%S!Je}+-H%HspCk-D=vPD z8z8Gq-qa{Ak2JX)RlM8na7E(hg4@Hp+*-w*q|lU!0O0^5Wu{tHF{Ie6Oj0b|#@q6R zdLAGf*L&){?;`!D=K;(Ecu!_#sA>u6za)$F55xT(u9*NiO84QFGd;XJMFVId1s3E3 zNC2P7%=@ZZPYSHeCIyDOJ)8%}k0--nV$`PAUnc!m6acgX+?SaKRdtd6U*?eh(RPO? z)8@4DHs0>x%>Wa;^WDq*?j|FArPeNZ(zS$EI_W=cJB;SZ01{RZua2$~;xSas` zz5s)Nz|VMadI;4bj?;(}O2oh!5coU<4!{v1svM+5M3s?<5jY~rth_FO0$)mof66aP zN{p8BD^2-LNr^&62r7c0QXCWQ)nv=jLo!Ema-F=3v*XoW=*ubh&pD~=GfcY{^t-zA z=pkEsc1oe?w&|RvG-s&zgNm~X-*}V-efC11Lzr)ZSO22$RSJYJny=%lYCU|q!)4<< zu>eIr#@YUi=M*Bm=tim^Q2|$JXpu z3A5R}`i{c(uJdU&yzGm8Y^(j*{`9gjgL?tGOn`Q2Kz~t=D^&cg04+iS1n+?077Vo5 zs}CzcpSqt0G60nLfVTMqT~&beVA5i*QO2ZR7_Sq?^P2evMY~DGKUCaOU^k%I(0?oR z-+^Jj^6G;MtX%grY&^guAM9y=*xO!MmzIBr!dCSH`>(PNb(;G>%GOTBT`KM=w1)w0 zhLDF4@&w}^@is#HDZCfw5MH*&N;Fhp;!+=Rmp^d_#hcd)-hBmcu!i@5!gNycP@%d8 z=qe1E3q$5(s_V3|LZNzs&oN{#@?rs$Q5wAK_~SfM663YRE*kV$33>vk9fsw=Fq5p; zA=)S=LAn7b!)R2`e7eyHp+baUEWSUHx*z&P)?_f$tRC1odCeMeK`octDM?ZJ9qxv^+vIK-vn}rEfk$Os<&rd#I`a8xBAaDSfO#h>Yzz8c%=$KP>Oe_~ zroWr;$;V?6*8E;a9fTwKSMo8;Vk93_aD2G?^SRME20xaf>GZu&(I%Z+j;3*GiBksY*V{O2`SGP-Vsjta4~bzH^x+SxiiUSy|* zNv}UP1@9?+Bc^3*XZ8M`27|~3e2}weZ`Quz2W)#&^RU*%Jq>Xp8(+Hc+lBX6Z5b8b z@lir~tEHzQR%F@w$g6oDjw+k@T3n|kIMF6a;i)`1nBalmzE&A;fdVSG=E+AjflI=tJc<>F(2LUT}X(*3rL4AJ-H;& GX#5{8JhP?% literal 3022 zcmZve3se+U7{~9o4x)yZWj>EbGzHPX1vEu_?DAfGu!4)I84c`!tGmOpyC6PNPi80W zWUJ!iM4rYtNyqX@rXuQy&$3Vh#gKfEs3|6CJ}UHd@14Cnu(Idu+5gP^zwiH>J9qBh z7~WTFvI);el~9vEpw#9QjlmV%(M#t37rrc zgLFDcx*`n}QHoA3bCZQtXlVB>yWrSr_2S#h!(_Nif}AdgMa)T7n;j;n2j`0xSG;<%lFhp#Bxn4O7k`|$anC6lvhjSEvr?texfJp)f1;!_|HsK5sJE*&|y7vD3-a4iYg%#ca4N1 zBu8*fGNeZv;{c2dgB#$RewswLs7Ys7z*!P-*9_cQ;Lgchv!X8H06*YNBq10l#9Ewo zfXUweBYpe-g8TbHM>U|D1=QdG+$s+`I-p|#mVSzSk4E&FMk0pc2)&s;EPxbmiorMK z98GDp_?%}cwKS#AeDL23{uMZ-uOg4rl&}nzl57_oyohIZsyF2w-;@h<&U39+(O;Ff zzz;^NH&{nm#;GSRGM0KKeq-VirHewb&^Z`7hhn_39zB}!P0AsBVM3vhmG2Vba~(F` z6%H`P%ecsw@iHaC6K=Tj0!`sFt-?^7h!+silBGgjA(N~3-Uqt( z$E+JXdN^hMw%}RTkpNS@to6RE%?fL)5&DagT-l6LSOQ@lVG?;i&9FBAV!s`G#@ z!+-!7@B*f)We0(j>NcW()xjPtfN6}z5BmAyw9v#+YT^?X^ppnO26Phw^$BYDAE&Zr!r6i4DmPFn;%av($YaegoS9E#uXm{U5E$P); zzj{uRUS*yb%E31V-zYCURAj6yN{g90sIC=hG}&CZwWls6EPwY%X29DQ<0Or=aYEiz~}liH^u9*Q(2sq;8?y zT5;Qw~R3aq*2V_iD;3EZY;?8Y0}TI} z-tQSMe`k`U;8=m|IPiTn-DZX}SGd0=p? z#X(UR2XBD3tOe?!K06&8MA5-THKnmSqqV45980x!)k>#0GA)%#(aiUqdv-Xv-W%v+ zW_8V)v(}gW|NDRJfB$>$f1h(#%KXhu(~66Wm-&i(nwD{}TGO-|m!{RBO#o&Cd;}N^ zxB>Rh1o+tHx!`XA{tD2;WI5nzTW;%jfM!4amD&0^7W<=(0g>s4{;mg{7U*X%6w0AuIe*cUF(vdQT)Ts{VUoR9KBImcoAD}eD9t#T0qUd?F}=;Z+Y^5Og=&8q+cpw|d066c30PQ>$%{Y^R1waZg9~cI3T$K;zCQ=Mu^v42x zlwZcZ#q0^qnIw6}#oS&6@KJMTe?GvN7+)g5*i;V3f#w)?8S}6D)x4QoK9q6Zj3dc{ z@|6pIgVm?T=eS%a=7D=-7Epko{#4Kp_jMVt82B>4bzKeA1B{~`;CgQc?gDlIyMR5w z1HdD|0pKa%2+#{Kt{2h13cLxN0^S3D0elFY1AY%UpcfCM0O`OeAP3;Xyr}t;F94Wh zwKm*4T$31pk6oX6R{G&Gu91>mi7)0{>4*E`UWq2-o{lEtx<`}oj75`i-$j#gKSq=B z>?m2JIY;V)$)KF_oGBmSGS-b~va}&&Jj2TFN@CzSQ2HPT#TPS#jC&)R-H0J%tVhZ& zQhbs6U@|DKkv1RUvQb0GxWCod;dZPa(PWuJ$asE~U8L9}^@WekI&~#JxaZXQ<&n;@ z@thm$S$Mrx{dPNb#=~o)$^P)z1btqB zz8e60y`J)@S>i)w#6yh3E8tt3D4E1J8k~4dL;{ z3?ch-)@OTsSCY5C^!ogV&L>iRj^yKisy?$$^5K}QqpYpvfckb=51MsY)mwY*+=_m_ z6RZPxuKBJ@zCH>lW*h0*PQF6^wd6~>@I-w=lhw8h402nmpVB%UX6LBv2g9^gZq!; z5cJO)%Q4m7201V$Y0iVTeC)BPeif_AGj;!zK9w)-MaH`TxWl5kcI;aSaIdkS57(Xg z>O9h>1*itnfp8o0%9rwwF7w^W?uX;V0?HR<1oJi@P;sgAQii^AfN|Juz?$z0lq(zF z56l(yRUiHEvA>6LyaIr6P+$1~X~rAwLq|U`9^n46+i>1oZ@Udxb3E0mHRiZuEt$Pf z#iG_&$>^JVA_k}j?E9QD`eL07-_z{h0NCfO^qbJn^GI0-KwI`PPoy^jofaLbpE>wr z;-N2&%P}}E=Mv37b6scY*mJ>oH3IYzsh|F6OZm+J$Duy^xo(_uct7XDeH-4-y}@|x z{rpWy`J`X2JM*S=_!|lR@nN30C!(#Jik0nIfHBiIeX-A;E8dNimjZm~oAZpeUmR4z z6JE!-2MPej#piNzo>k_JYeib+b^&PSaz4P^l>>~o3<&qhvGM@slewA%@HySz-@gtm zp==Z%-ZHQ803YUt-)YSMMvF%?=xmVZUSZxCXDPskKGgWV7~jr66~=!njNcK)*M#wN z!}zo?-uSG)pYI_YpX*Qwo;l+lQgLwIj(pnR&$U)E=AJsrmTORPvA>`5QaaS9U*`Jk zh5mlEU+lgq`?e+HnsF~Hn{u0tlBvDTmj2js9JbV9OCM|%xGtneSZ$`&^7jk&^FCzD zcTcuntL0je=RVeWBX}r&?8-~3Qv=dN*&ZM(n8Tf3<< zFwJ|gcXH!^yD800qMeuAcO>^edv*K}Y0`PwUxY);XTG<@>+9AN!Im4rUo^ zx|bNip2Z~1hha>)d>Hw4rr&(u^cuH5zO=N7vzk)XS>M!HyJk&gdt*yyLnr&jl?Uot z>jUjtCAmq<+Q?P=YnuYvI`rr+(Kg#saCM}iLq?doUM|{2$vYx>FZb&66@8x5<&3N; zPbl;@w6-_#`5gmJ@;lsmc4?_-LB@NvXnQ!5g3w$=N^Q|kEo<$% zab2gk!Qa%_)gEBPT_R4&|4<52di9NpE(nWwtk=y@Lu+6J4;6*^$?t$dI${trXSE`2 zwo(5&!aNq32`E}KV|7ajqWFerXJl-WjQv8dzDLn383i|mIr63a#YfsD_8I5bV+#1w%|EsL)5bpm{Bi58 z%;OoZd>C=r32aXJvGjjGhf9 zPcbF%=R8h-9&wrx4ii1jG%YAwwzM*2J6*Kz$mp-j=qF)Yq?jYH)w5{(1<_}-^@?82 zHdl1)mL9!8^n2J&5dAT>g`)SdohtfI*-jVzVkpcd^CS&Hwn7_eL)rzUZ zP_7hHHE)SEp;e;2E@J{RW-~NbE9MSr=F#~=ap9o!=!?a*itSQyb+fG$*KW&GWz`I( z<|ffjO7;}VUIeCHF-z&m411Nh%&^yp%M80#TnM{I4@gWV+jSCyC1JL!s>>=&m)k^p zTe2UN?C0TfyJGs_GNvLlcvbZRQ*)s+FwU;QDdJY=P@o#Ep1!tIN%#KP}q# zB*|K4jb{TAyS+Bw5eF_yxs$m&TX?Mwx@!)DdXf zRQ(@J0VxhOCktcc1pbLS6O)B)ZwguY#E%lI%{Co+bj&*}hw4|54 zL0PC^7Jto^&4V|M3Xk+aJo)vuD|P`g7&n{wa->KckCMx=SmMl0d8fpO)^?!2I2MX_ zmkd8B!(ZujIVu$M8l1$NwV+4h&04Tq;vX{?@lt(pEEjFNq)n8xg|NL|F+70rM=`E$ zNc>xDAC&lWY#$Lfib0S5Epc;yq87TbCwugN7I!_{L*m}d_OQ6I1$Z!3eR13@+Wj)( zM>68q7^+(_=P{HU#|o;dzBo3E_JEA|L^9H#dAnjVscBY&e-pP^4Spc*iyZ8@B;Zu_ z=x<0us2b!g3Dp{^FpGkrl_WP26uzU2=lJGBV ze+ba^^74XeI5aJCz;) zlE}DScxgyP;2>fovC<^sC9%mQ5+(6&lSr0CoF!(o%BnJs*F?Kl(ms~-R1EOCVlps5 zBBF;lnjB%2$?aaxj@50`VT zB==q>tZAIw3awr|#p2ltdZk4hbo^7(%_K=aV~%h^l0$pIzGBWs%VG(v*IRTotWy$A z>ljJlO1PZylEP#STBd1|!Wm{`&fMeDXE6+~{q_HxOeype>ig z?UIO_-ubviKMk*`cbGmFODZOX1Rayq$4ue{NyWOM=Osyf%OqZw;j>NRRT*As60gbd z&?29}4Pf@1lr-dW;D#+yZ@YdKP>!3?yt!JOTgCY}$RCBsKHQ}ID8Y3W$w+r2)-)sv z0X-vWM{Q$_Yc)UgcuPCatP&^Qfde2v43W3-hK}&%G1=SL;kBa6aq}Bw;FD;k%D|Q=xHm(aa^3SAk#zS#IVJfzfyDZ*2;1i!@5!LyXmUfQu=pt!66#Fq(zDJDZmzYbRxm2{RqJ0D8tPuHhlx+Nk ze20aWKz)8;Ne-2?@M|jC7nZ&rDM+s{Q_wBx*p$KGu3X;~pQPW4&YhFhuLSe(gGPs> z_Zh~{oh}_W^1f2T7?569x6a=l^tBeB?K<4Cd(M&RKYZ!p%1>7t#w2B56}TzrTUNS9ci3ROO<=-?6Tx?JfSM&?o&oe@A0oN6^=Ic*~>X&W!)<(Y+6@KUM$37fTJ7e$v2a8gS8Y XIlly)4fVN3qJ7xV>(Joi4bOiAo8t77 literal 9812 zcmeHNYjjoBwchh&AM!j95(4BTCmtXPK^{H4Dp9VDBnAjzq9lL{!hs|b$jc-uSSXaY z_cHVZQBkx#3~jOAs>mBeIHg$VwIUTP!ezA7VoL=_vDNxQbH8uxy>KT@qW9WgcXSOt z)|_j7bFR7OT6^w&7~}_Qs)y$0<`xHr2Mi;nN2y^LyG+BFgFYS@1+WRw7l;LJ1qK43 zwVLk(Jr2kRXj=eG1)^+lE(u^`9|NQV^viX-18jOO12Wgp^IV(FIq!z9=NV%%-~w&~ za%@@ep$l}z#rPHiQvll2E)B>6xE|X&U;uD6z!Xd(b}sJ_B6f#R7>y3g89$0Bp|vQ_lvX zfwncL3n$T>eAaHwZ#&0&t>?auFXmkH+xp`Br=z*pPUd*-9ofZqGROB%M|Qlk9nE!f z%(b`Y_Qqh+DyRG==*U0c%N@=2=wy!HBiiok#K31s^C7m1uS+L$yc-?a_3UJ>mt(HI z_}UwTNvpV09X{I5c{`b7o#`lMev@=G*SnKBK0n&7z1Z6ugGsCXuugp)AG~wAe({m+ zJsT+nZ+{>ujF;?QEXU zQfKqbd1v#{Uop?PwS7nT%9#&mz0`bXE}4TqfWA}T^bYaNd0yHd^Tm6@byfr1Kc9ac zi}Tz6o5sSkqYvIcu0zm2Yb@8~^Ub}o>G&w~dxExXdYpdrxQ>;%`DcvjXO4G~>l6Yj zY?)`rv9SPi$8k2EJNf!~q)jbQ3ZwvSZK!Ks+CPTW?_j4Nt`iMtUz{VDw;KT+mwsMY z3km?n;k1FO>KW&?4c`yUEBShie%Lztt{`9gAdmOAtq&7pL=ND#=d}&@&GUBJKvnDM zUY{}d+1H+Pj%8zvInn2?=jfZ~-vuZKocEk_^u;>a_D*wrKH%K5=2v5!&m-sfo0GO2 zW1cAA12oxkd*jT(|0N#!;<{Xe>vAt0`Dd=@*c@jrxUVXJKH3|nKiYEsUV!V6&vBj` z_uO`zd*QupJI?c9yw34N=-Ma!^4ys>&EYpV{jo7myb~Rrn~s$|f73H&`lc_AIdjE# zBj@t~Hu~m1JGw6}lF-`zw&5Mf1{fDxXYFeEY2i8OIqr)#%;$ZVTUvOJXrsqzGxM{S7JYtBf3z8H&(V%|i}RG}ljr;A zPrtNva$+z?F8#7+Oxl*c_C=ZCnXvC^_r2|&->n?ydx|~33EBJYp6A5##wWy*Djb{ zU$G@Jxax}YAvM)voRh0Ai@#gM#LrMm9+;OW!ez{EBGcKYiyTtEGjAv;7_lW{;-~5h zlG-Gx4@S)HT7C$2u6>G^1zsVEsbXxA)Q2VY#fXXDwU)e-#ACL@o0P-8V!SA+yCwB_ z#O$Z#ljNPV9Of5KDxt%HVr-SvQThWa- zlUFRpen}fGX;UL+iI#6CZ=B5=TT0$EF%C%D3`tuMF>lrKBJz-NoML9tM8yk=5s|d- zN!nu(6Gv>xPm))!cv(f0%f`^*JTZPIX+M;-mm=nTEk{UPVL6;wa07XbV!R@0pGbO- zh}op&-sEl2JmqhZ7{8EoucVKRn2WWXOWsedg(nu|kE6qtVjPzA>m(gJUZv&fBu2DD zbsi6haYWMZko1KS^Fb{yChvsiO{Bj^#rUP9FOl@eBjyGz|A4&nnm3ueuo(X(>0wF7 zhBs;X0C|@+Pi62YV!SHpKa=z`5%XCsp9RlM)Vyi*w^fW^N&4H8{&~dQX3IVyFVp6g zsC8cw<2CU`i7z8!?$dH#@kz#W*IuO7Sg=n19vsY7)0-hw6Yo z730_9yI*`yN6gQ({0w=AG>?gKOOzOIi0@hPy#mG5$}h>ZN*K1nRJ$cXjN{^aReXPh z;?c^xWM0%kPM)f$_?NR2;=3prF`)L;iU(A;p_k`bRtN8_DE9{&{grhMHNhso z3TcKIrzK;JWV{LcJGAl_+K2fn8dzM<_flzac6EigQ7D?-QZMd(%6HDB+KQUG+NwF+ zT&*_V2&GOdPtnt_l-VM2qb|UHiMY=xVXbrtKv*~E%hzM!aEZnkZohit45#On#$rh- zm85#et8Dph_>C@rvDsCkXR+@t(TkL!^}%~|qNk=8=0!$y)%KNkp(Z(my+>+^+ z=p*d=Ni-ufvn2*stl1nOG3o3FNeoIsv-vHFDP=!QV(P6RSu@pAJH%KoDfdarBUoyu zRyJa(m=%heIkBKnG53q{u%tXGDZ9Zupp|`OZlLqA60@Csk;EKhKS^RPvM-U?7~7Mo zTW&cn#^chnQhI(Lo=#|GB|OEdu%}C`3VWu+s<3BEEW&O!DqDsc$A*<3Dh zne10dTps)TC2l(VwGwAt=`55*l_6I*F;+_Qo~-XyMYIasdV)g zW0fSoEXgOK;LF5PPLmj>?@bbCMcr?zWsoVxYDqpL$$y7ImR3HY0fL6-jvp7b;9xN} zOYh;*dnxRPXytL*tBZ3?;x1ufx9fU|#|?r*=QH9Ott|>+j?Wa!*G({wPgG__65m@1 zlO#Sz3AagnHH22r$S{dNk1-SF)MOtc2`aVml2Aast0a`O?=A@|*!Pfxr`h+CghTAT zl5kE1*SByO(>UL#m&BVTu^Mucv)b}U%-n; zZA84{83A{0*BbE@{9|fX*%r^jdbKTYr8RG^+qGUiye)3mqvByc+^(m^v;Hf>8p_RW zFzyh~M)917{Fo(oWqtH)ryIFWJQ3yZC*rZLK&unmY+FAM>t}44U%Q^O%4i4tDq**H zn5d|d%~Dl+r@sbo1;%*6D3SP!c&|ggXv_TgOq`~C zd?Jb1RI@v(izF^mLaZd>+%S?Li9c0BH|d_Bge2*nse}~it`0e>w{%~jM$#k+xeRT} z3vZeb4s9K-e-Z_CKz-s6O;qw!ah;c_M2I~sG5dx*JcfDrt6d{A4zVU7QO)aySiibv z&MaxDs%@&2q>y95{&ng-=;tDXrikkiaUF&@*b>iTkxd0$=L%GqgZ)*Femm4Yab^!I z6cx<3ZHHOqtvP9o=NZIfUM)#m91#qtv0t_-hSD-|4HH)tVkoo3wTxkmT3@X_l74IJ zn*3EY_0<(M6}3$j<%prHBZgT26`xs%vpsqW!#TomCQ6ceJ|5~97!r`Ai%i*Iow6|t zn<^S58Ar5koja;oQjENC_{wbAoVmeBN|v6OS+g?X?V=Z>=l2eW+Z;(K(6xSJ(MM$uY?-$4!k*=8jy@0$e@nX<7i^r{ zG`l(!_;^$B-{U_2XovTEm!}Hnv_3l6L=Ik2x^;W!Z~c4BfA(1amS@VDdEv1A zt34DL9FtwSf62kU&9x1~bDNrf7Y={&(@ z(CFi5a^4D~L*H&1?O`iBQ^>@_6%1fJJX`S>4Tcu*=DYJ=5<>XULz zu(4`RBet+(`R4u?b3WX+@u_)d%3nX62mfz{-I59{3%gx61JxLN8#om TODO prestavi v main*) let regs = Processor.{a = 0; x = 0; l = 0; b = 0; s = 0; t = 0; f = 0.0; pc = 0; sw = 0} let memSize = 1 lsl 20 (*2^20*) @@ -84,6 +90,10 @@ let getAddress (state : Processor.state) : int = (*execute format 1*) let executeFormat1 (state : Processor.state) (mnemonic : OpcodeTable.mnemonic) : unit = Processor.pcIncrement state 1; + (*debugging*) + Printf.printf "[Izvajalnik/executeFormat1] Mnemonic: %s\n" + (string_of_mnemonic mnemonic); + match mnemonic with | FIX -> IzvajalnikF1.fix state | FLOAT -> IzvajalnikF1.floatF state @@ -98,6 +108,10 @@ let executeFormat1 (state : Processor.state) (mnemonic : OpcodeTable.mnemonic) : (*execute format 2*) let executeFormat2 (state: Processor.state) (mnemonic : OpcodeTable.mnemonic) : unit = let (r1, r2) = readR1R2 state in + (*debugging*) + Printf.printf "[Izvajalnik/executeFormat2] Mnemonic: %s, r1: %d, r2: %d\n" + (string_of_mnemonic mnemonic) r1 r2; + Processor.pcIncrement state 2; match mnemonic with | ADDR -> IzvajalnikF2.addr state r1 r2 @@ -119,6 +133,10 @@ let executeFormat2 (state: Processor.state) (mnemonic : OpcodeTable.mnemonic) : let executeFormat3 (state : Processor.state) (nixbpe : nixbpe) (mnemonic: OpcodeTable.mnemonic): unit = let disp = getDisp state in let operand = getOperand state nixbpe disp in + (*debugging*) + Printf.printf "[Izvajalnik/executeFormat3] Mnemonic: %s, nixbpe: %s, operand: %d = 0x%02X\n" + (string_of_mnemonic mnemonic) (string_of_nixbpe nixbpe) operand operand; + Processor.pcIncrement state 3; (*povecamo pc pred izvedbo ukaza*) match mnemonic with | ADD -> IzvajalnikF3.add state operand @@ -169,73 +187,85 @@ let executeFormat3 (state : Processor.state) (nixbpe : nixbpe) (mnemonic: Opcode let executeFormat4 (state : Processor.state) (nixbpe : nixbpe) (mnemonic: OpcodeTable.mnemonic): unit = let address = getAddress state in + let operand = getOperand state nixbpe address in + (*debugging*) + Printf.printf "[Izvajalnik/executeFormat4] Mnemonic: %s, nixbpe: %s, operand: %d = 0x%02X\n" + (string_of_mnemonic mnemonic) (string_of_nixbpe nixbpe) operand operand; + Processor.pcIncrement state 3; match mnemonic with - (*aritmetika*) - | ADD -> notImplemented "ADD4" - | ADDF -> notImplemented "ADDF4" - | AND -> notImplemented "AND4" - | COMP -> notImplemented "COMP4" - | COMPF -> notImplemented "COMPF4" - | DIV -> notImplemented "DIV4" - | MUL -> notImplemented "MUL4" - | OR -> notImplemented "OR4" - | SUB -> notImplemented "SUB4" - | SUBF -> notImplemented "SUBF4" - | TD -> notImplemented "TD4" - | WD -> notImplemented "WD4" + | ADD -> IzvajalnikF4.add state operand + | ADDF -> notImplemented "ADDF3" + | AND -> IzvajalnikF4.andF state operand + | COMP -> IzvajalnikF4.comp state operand + | COMPF -> notImplemented "COMPF3" + | DIV -> IzvajalnikF4.div state operand + | MUL -> IzvajalnikF4.mul state operand + | OR -> IzvajalnikF4.orF state operand + | SUB -> IzvajalnikF4.sub state operand + | SUBF -> notImplemented "SUBF3" + | TD -> notImplemented "TD3" + | WD -> notImplemented "WD3" (* Jump / subroutine *) - | J -> notImplemented "J4" - | JEQ -> notImplemented "JEQ4" - | JGT -> notImplemented "JGT4" - | JLT -> notImplemented "JLT4" - | JSUB -> notImplemented "JSUB4" - | RSUB -> notImplemented "RSUB4" + | J -> IzvajalnikF4.j state operand + | JEQ -> IzvajalnikF4.jeq state operand + | JGT -> IzvajalnikF4.jgt state operand + | JLT -> IzvajalnikF4.jlt state operand + | JSUB -> IzvajalnikF4.jsub state operand + | RSUB -> IzvajalnikF4.rsub state operand (* Load/store *) - | LDA -> notImplemented "LDA4" - | LDB -> notImplemented "LDB4" - | LDCH -> notImplemented "LDCH4" - | LDF -> notImplemented "LDF4" - | LDL -> notImplemented "LDL4" - | LDS -> notImplemented "LDS4" - | LDT -> notImplemented "LDT4" - | LDX -> notImplemented "LDX4" + | LDA -> IzvajalnikF4.lda state operand + | LDB -> IzvajalnikF4.ldb state operand + | LDCH -> notImplemented "LDCH3" + | LDF -> notImplemented "LDF3" + | LDL -> IzvajalnikF4.ldl state operand + | LDS -> IzvajalnikF4.lds state operand + | LDT -> IzvajalnikF4.ldt state operand + | LDX -> IzvajalnikF4.ldx state operand | LPS -> notImplemented "LPS4" - | STA -> notImplemented "STA4" - | STB -> notImplemented "STB4" + | STA -> IzvajalnikF4.sta state operand + | STB -> IzvajalnikF4.stb state operand | STCH -> notImplemented "STCH4" | STF -> notImplemented "STF4" - | STL -> notImplemented "STL4" - | STS -> notImplemented "STS4" - | STSW -> notImplemented "STSW4" - | STT -> notImplemented "STT4" - | STX -> notImplemented "STX4" + | STL -> IzvajalnikF4.stl state operand + | STS -> IzvajalnikF4.sts state operand + | STSW -> IzvajalnikF4.stsw state operand + | STT -> IzvajalnikF4.stt state operand + | STX -> IzvajalnikF4.stx state operand (* Control / IO *) - | TIX -> notImplemented "TIX4" - |_ -> failwith ("Mnemonic" ^ (OpcodeTable.string_of_mnemonic mnemonic) ^ "falsely flaged as format 4") + | TIX -> IzvajalnikF3.tix state operand + |_ -> failwith ("Mnemonic" ^ (OpcodeTable.string_of_mnemonic mnemonic) ^ "falsely flaged as format 3") (*execute format 3_4*) let executeFormat3_4 (state : Processor.state) (mnemonic : OpcodeTable.mnemonic) : unit = let nixbpe = getNIXBPE state in + (*debugging*) + Printf.printf "[Izvajalnik/executeFormat3_4]n=%d,i=%d,x=%d,b=%d,p=%d,e=%d\n" nixbpe.n nixbpe.i nixbpe.x nixbpe.b nixbpe.p nixbpe.e; + match nixbpe.e with | 0 -> executeFormat3 state nixbpe mnemonic | 1 -> executeFormat4 state nixbpe mnemonic | _ -> failwith "invalid computation of nxbpe" - (*execute ukaza*) let execute (state : Processor.state) : unit = let byte1 = Processor.readMem state 0 in (*read the 1st byte of the instruction*) + (*debugging*) + Printf.printf "[Izvajalnik/execute]Prebral byte1 %c = 0x%02X\n" byte1 (Char.code byte1); + try - let {OpcodeTable.mnemonic; OpcodeTable.format} = Decoder.decoder byte1 in (*determen the format of the instruction from the 1st byte*) - match format with - | F1 -> executeFormat1 state mnemonic - | F2 -> executeFormat2 state mnemonic - | F3_4 -> executeFormat3_4 state mnemonic + let info = Decoder.decoder byte1 in (*determen the format of the instruction from the 1st byte*) + (*debugging*) + Printf.printf "[Izvajalnik/execute]Opcode %s, format %s\n" (string_of_mnemonic info.mnemonic) (format_str info.format); + + match info.format with + | F1 -> executeFormat1 state info.mnemonic + | F2 -> executeFormat2 state info.mnemonic + | F3_4 -> executeFormat3_4 state info.mnemonic with - | Failure msg -> byte1 |> Char.code |> invalidOpcode \ No newline at end of file + | Failure msg -> Printf.printf "Cought faliure %s \n" msg; \ No newline at end of file diff --git a/ass2/SICocaml/izvajalnikF4.ml b/ass2/SICocaml/izvajalnikF4.ml new file mode 100644 index 0000000..80db3e8 --- /dev/null +++ b/ass2/SICocaml/izvajalnikF4.ml @@ -0,0 +1,155 @@ +(*A <- (A)+ (m..m+2)*) +let add (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.a <- valA + operand + +(*F (F) + (m..m+5)*) +(*TODO check!*) +let addf (state : Processor.state) (operand : int) : unit = + let valF = state.regs.f in + state.regs.f <- valF +. (float_of_int operand) + +(*A <- (A) & (m..m+2)*) +let andF (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.a <- valA land operand + +(*(A):(m..m+2)*) +let comp (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.sw <- (if valA < operand then 0 else if valA = operand then 1 else 2) + +(*A <- (A) / (m..m+2)*) +let div (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.a <- valA / operand + +(*A <- (A) * (m..m+2)*) +let mul (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.a <- valA * operand + +(*A <- (A) | (m..m+2)*) +let orF (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.a <- valA lor operand + +(*A <- (A) - (m..m+2)*) +let sub (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + state.regs.a <- valA - operand + +(*PC <- m*) +let j (state : Processor.state) (operand : int) : unit = + state.regs.pc <- operand + +(*PC <- m if CC set to =*) +let jeq (state : Processor.state) (operand : int) : unit = + let cc = state.regs.sw in + match cc with + | 1 -> state.regs.pc <- operand + | _ -> () + +(*PC <- m if CC set to >*) +let jgt (state : Processor.state) (operand : int) : unit = + let cc = state.regs.sw in + match cc with + | 2 -> state.regs.pc <- operand + | _ -> () + +(*PC <- m if CC set to <*) +let jlt (state : Processor.state) (operand : int) : unit = + let cc = state.regs.sw in + match cc with + | 0 -> state.regs.pc <- operand + | _ -> () + +(*L <- (PC); PC <- m*) +let jsub (state : Processor.state) (operand : int) : unit = + state.regs.l <- state.regs.pc; + state.regs.pc <- operand + +(*PC <- (L)*) +let rsub (state : Processor.state) (operand : int) : unit = + state.regs.pc <- state.regs.l + +(*A <- (m..m+2)*) +let lda (state : Processor.state) (operand : int) : unit = + state.regs.a <- operand + +(* LDB: B <- (m..m+2) *) +let ldb (state : Processor.state) (operand : int) : unit = + state.regs.b <- operand + +(*A [rightmost byte] ← (m)*) +(*TODO*) +let ldch (state : Processor.state) (operand : int) : unit = + state.regs.a <- operand + +(* LDX: X <- (m..m+2) *) +let ldx (state : Processor.state) (operand : int) : unit = + state.regs.x <- operand + +(* LDL: L <- (m..m+2) *) +let ldl (state : Processor.state) (operand : int) : unit = + state.regs.l <- operand + +(* LDS: S <- (m..m+2) *) +let lds (state : Processor.state) (operand : int) : unit = + state.regs.s <- operand + +(* LDT: T <- (m..m+2) *) +let ldt (state : Processor.state) (operand : int) : unit = + state.regs.t <- operand + +(* LDF: F <- (m..m+5) *) +(*TODO*) +let ldf (state : Processor.state) (operand : float) : unit = + state.regs.f <- operand + +(*m..m+2 <- (A)*) +let sta (state : Processor.state) (operand : int) : unit = + let valA = state.regs.a in + Processor.writeMemAddr state operand valA + +(* m..m+2 <- (B) *) +let stb (state : Processor.state) (operand : int) : unit = + let valB = state.regs.b in + Processor.writeMemAddr state operand valB + +(* m..m+2 <- (X) *) +let stx (state : Processor.state) (operand : int) : unit = + let valX = state.regs.x in + Processor.writeMemAddr state operand valX + +(* m..m+2 <- (L) *) +let stl (state : Processor.state) (operand : int) : unit = + let valL = state.regs.l in + Processor.writeMemAddr state operand valL + +(* m..m+2 <- (S) *) +let sts (state : Processor.state) (operand : int) : unit = + let valS = state.regs.s in + Processor.writeMemAddr state operand valS + +(* m..m+2 <- (SW) *) +let stsw (state : Processor.state) (operand : int) : unit = + let valSW = state.regs.s in + Processor.writeMemAddr state operand valSW + +(* m..m+2 <- T register *) +let stt (state : Processor.state) (operand : int) : unit = + let valT = state.regs.t in + Processor.writeMemAddr state operand valT + +(* m..m+5 <- (F)*) +(*TODO change*) +let stf (state : Processor.state) (operand : int) : unit = + let valF = state.regs.f in + Processor.writeMemAddr state operand (int_of_float valF) + +(*X <- (X) + 1; (X):(m..m+2)*) +let tix (state : Processor.state) (operand : int) : unit = + state.regs.x <- state.regs.x + 1; + let valX = state.regs.x in + state.regs.sw <- (if valX < operand then 0 else if valX = operand then 1 else 2) \ No newline at end of file diff --git a/ass2/SICocaml/opcodeTable.cmi b/ass2/SICocaml/opcodeTable.cmi index c7ab3a0b4bd43ae2d5f3fc9907bab4c2afaf0bf0..5d89792a3a13186742a87a74dae3966c99171d43 100644 GIT binary patch delta 269 zcmca4u~|~VIWafK(9+V<)4%8*RREFbYjJ z=G@FEJo!1N2IJSs0$kRNUncu-1v83FUcjXz`+dQI%@bHG9VR$1v3`BX;K1+=!Td4# zC6|SX=!F9Z9S&?}u|r7w1nOC=R$Nk)nV0U55dH--< zGBSxl4RS;1_yaUoWU?c-q%GVQ|mmy_3WF9iUF177F= delta 176 zcmdlic}YUSIWafK(9+V<)4;^2!vqH=)~^p492kBgn7=2# zvP6jW*fLxqI!Ly!cL3Tab)At5I5g%|UJFhfQfk^l)W1d}MO zq!LO{lz>T4pb*M)0KpokV1>58;H}caR2*rowX~^pv{Mk$LZ`K;fa&+#yF1NfcC>#0 zcjlXW&VE1l?7qFbo0sHP)WxP`Wo1RuGtz~y%gcli(+EFs&4C69&- zIkQ}6n$$OOzZc4d?t|`!B2W}!ZXPrrs)QCnOQ3qF5n2wdfL21Qp(mkr&@<3RXfw18 z+5zo^_CPN|KZbq+{S-P3y#~Dj9f#h8-iF?R-h=)Goq;}t&O#TUi_pKI%g`054;q9I zp9tB|VCc){;ku7W!}b5Jo9pv+eZIbEy-a|4CzK%N;2whbvZ33d>73v)pmER*&?2Y> zS_~;4p-6@-Xd;B|EI#V%>tlu$gN{KrLMc!sR0DCl3-xcWmF*`6v@enEzZlTYHF$h{ zzohX3()*;JS0&r{^YC-+8ZS|LuWG!Y^x_)NlwOy{>pEM4ObmtLmE8zH^v8jtr2*DTO@NoZTFX&;F;en#hgO?oAo=kAc+ zGL1J%dO?jhT6)~4+H>l?^8V%aCXL5?mOb8Q1E1r$XYZ88OO@UzjWV zjW=F;VU5RU8b9Y~JU;8#`;NxrGmE`4jWGAp*R1i_3+Q6}7NUvPu@jB=J{-W{tI|O??2Lo%~Exn$89-r&H&-wi4bCBni zugJB&zW#X@ay|5}BSzlFM zR#WnC{ z)aSQ`LQNhsCO;!B6V$EB+2a~RRs2#YB=S5gCBJYks3cKM!Fd#1qTqVhNRweZL*@RsW<^SiK}{2j zDcDKD9j-B5hC7*x`NN8Or9z^Hg1afW-!*b%_$ouqK2+vGg`$>%2PycvYZS@wmkhP} z{pIB4m7>2=QAfek6#ScOL}hrMsVrQW=h8>ZDH<&ki&7sCbyn31r^w8p~z) z4W@cLDy6iTCv~N0ATyiH0@rAf;r$HtdeGQtL1BJb7~ERXNMPqWwI9cw zc8Df2tH^A0jZPVU7hHnl4=p--22)$bBV?{1bFFJ^lVKZEN&e8H59R{eDIO(r1DRW0 zW0wrKGc?IBRaQ8cOLdFoWbPod+cjR6;XbCa{Ze>KfDVYq$ov(Vzjcj+GJKbzuwM#L zKB%JtLwb+Qzq-b2GCaprxhyq{OC1-@WS%GUKdx~?hMzJN^GoI8MS?mdzDMR2vVyMh z8yPxGHG5PlQ{3Ze@i@I40U(jn ztGI%(lM)L93(yTDR+CjpRy`8@>FOs94EA{7m?FGyCh_-dD_KostwJ(HC2N@M^-G5H zau^&&VhveOlC=@ZaFuLg@Tvm6ila$9LDm+sb^%OQ$sT}%9KY{yUTy)Gypsg#y-3zU zBokF~h{+^X67M2F86?({b%d-FNHSIOCWDg{h^-KyY!XkA^%hyDk$g)fJq%_mFv{Re z5>J!$K3V6H&UuD))jyem3+=%xdL&V251h6HnIiT4wAVl8O&fz zf+b$p-zKr1?3>9R39v#XqZn-VL7Wm?v4+G3vXjZ4jHFg2Qy6UXz~l(FS%4ZyJVSN{ z+4mr6R7r@rE}tvK_6X1l676KqAiEezvq~b&b$i^HQn@HvNpz6?0ND?LT%!^`RR$gL zhZrsM7R7oJon%*$y$s+6l{7MVQi0y0*hFF@*^iLT%WShsS{dx|`;M0Ri(&_fXUTqo zY+h$^m276RSC#Y@#a7P1D!whrzCzzP9`}aB%i4y zm%%o_;2bWPfUhq*$eBq_2@?GC%uh<0>x#!aI@6*}Rk4}{^XC^-G%jvh5F_IhnvDP% zm*Vlx&OpL2vI|1-_(a7;s~>JpFRGeOEx(&zx5oLPXn*38Ve$CDI_>G7JYVs&b?x$j z5szP;`_9X|?Rb2wU!y(!uHe{(M_0ansAFkEMpjeDnRq;qFrhvD_U*;HYtI&3yEtOf z@P(%?e-w{T&&9tQPtS3pfITBwi@h*Co^QInSH4GA%c2{-0mBr`D5kQ*T(A(&jG z6)K?wjUQkV5GZK59YVntr=S5_aPU;q!c-k>!CG1>9b_s6s?0Q2Tg3Ez&)J=3GW&1; zGIYYyoyrEk&w9#SFcUebM} z2q{WpZZ2s)sg|^mw3yUPY9%cvtst!;tsy-@dYbesX#;69X&Y%fX$NT+>1U*$lU^ac zN;*V(o%AN@2tMhSnJ^VlR!!5M7ZY2#<3ei1G;>#g@jg-d;U6M4JG=j8{)J9rF(msVE zm1L8qka)a*9~c;5hSf;wBV9vEBh`}XN!;#|2Ddk;_M=1E7pwMP4Qb~ZJU+f(GI#;y zeLl#Gt2X{T{9LEO8>zfrgBMg@(%@Ojd*0yj{BVC;3?9!pdwUFCNO?U5kLQk`+imbh zDQ}~}8?C&(25*e=elf_aQ*GC(`&ff_o${&;-u2208@v?dWg5J%D6hld-Jra5gZEYC zO*eQvcAm3rgLk9yat+>1%F8o&ykEFxiNPC3ZHo-;>$OLhvMle{*G? z3ePhY^Qer%@|gvUg~bvCFCzFKR~D#nfU&s3A{CX4m5OFqfHm5cWhzWzEaCTARQdo@ zRbnZu8(^imGOEJKOtt$|#q4sX=8A`5-2&@QSI$%6H<{Y#QE62bJgITf0&6;~5?9u# z@IHomJZMt1q_j9zPF#~{g;fD-o-3EAZ~=3@gE;Q=5s`ouht=xJ#i)VmYksu=cpJ zTZMa>>i0|0TOw$ycof!eVEx{e+f?`-LBph9ilAbmb_g2M`>@WsvPXsIm`YKlW^t)K zVkNBeu>R%BmsI#~hSL2~h4dnc+AqEj>oV-1D-WnJ#8j?FWiZ7(9u|+m9tC@xD_>XP zM8=Bz9_e)xbVRIzod$cVE03!1c7|deG_j13cOlwf=fb|*mA}*RJq*SDN@X+eC+sA| zYS;y^D_r>}9al1zP}se^8_z)e0CpAZ2VME0j%yfeS6De?7a-Qau7%y~%8NQ~VQiy^ zrI*p$Caxc%9d-itYFB=$J7G1%w#TV7OH!X*6(OXXgKeSnfNIyuPX30;!jLI7hSI$*yB`zR$h>f|j3 z&uWl1K>!mWo`n4l?30wF>f{uI{Thricq_zHus?u(o{}j#`3Hf+r3PsZ1IU4R8ull! zFH@4MlP?)e(IB0w0ZfN@29AIeqU75;8O>n20xP|)XF{xlb1j_l1QzRL0)x3eNaq7r zoCUESPAZ%%N+LR$#$b^LrbcLk1uzHVSvWax?xv(#Ct>DdK37E>BY^Kfbi$bdr-G6i zokW<6dt7>zw;%$jhv)#)*Qkw`!(n-pMwxv;ar0A1%Zcj!e2pBDv&p8 z0B=HULkI|6LrI@b#xR(o2043%H$iVhJdelE?W0+XLeaU4{ayrH?0kw zDcd)4@z`W?Xr0dN&wpI=lzrv1{Wm@KMfLHQb~?%AB)>*y_HDsQ4;^0h#=)*7Ejjs# zuG7h6VA!b6?7r#8Pi3CDWA>W!ujU?mWu=`=<`vR^73-HI>ROi6G!{3vG}R<#)U?*u fwi3L5&92E8Ge3Q8+m41)@nc8ANtsIfEFAtXTnm?9 diff --git a/ass2/SICocaml/opcodeTable.ml b/ass2/SICocaml/opcodeTable.ml index 4c4544c..03dc20e 100644 --- a/ass2/SICocaml/opcodeTable.ml +++ b/ass2/SICocaml/opcodeTable.ml @@ -157,3 +157,7 @@ let string_of_mnemonic = function | TD -> "TD" | TIX -> "TIX" | WD -> "WD" + + +let format_str format = match format with + | F1 -> "F1" | F2 -> "F2" | F3_4 -> "F3/4" \ No newline at end of file diff --git a/ass2/SICocaml/processor.ml b/ass2/SICocaml/processor.ml index c28b621..2499448 100644 --- a/ass2/SICocaml/processor.ml +++ b/ass2/SICocaml/processor.ml @@ -47,6 +47,12 @@ let writeMemAddr (state : state) (address : int) (value : int) : unit = Bytes.set state.memory (address+1) byte2; Bytes.set state.memory (address+2) byte3 +(*popoč za pisanje instrukcij*) +let write_instruction3 (state : state) (address : int) (byte1 : char) (byte2 : char) (byte3 : char) : unit = + Bytes.set state.memory address byte1; + Bytes.set state.memory (address+1) byte2; + Bytes.set state.memory (address+2) byte3 + (*povečaj pc za i*) let pcIncrement (state : state) (i : int) : unit = state.regs.pc <- state.regs.pc + i; @@ -78,4 +84,28 @@ let write_register_int (state : state) (reg_code : int) (value : int) : unit= | 6 -> state.regs.f <- float_of_int value | 8 -> state.regs.pc <- value | 9 -> state.regs.sw <- value - | _ -> failwith "Invalid register code" \ No newline at end of file + | _ -> failwith "Invalid register code" + +let print_memory (state : state) (n : int) : unit = + let mem = state.memory in + let len = Bytes.length mem in + let limit = min n len in + Printf.printf "Memory dump (first %d bytes):\n" limit; + for i = 0 to limit - 1 do + let byte = Char.code (Bytes.get mem i) in + Printf.printf "%02X " byte; + if (i + 1) mod 16 = 0 then Printf.printf "\n"; + done; + Printf.printf "\n" + +let print_regs state : unit = + let regs = state.regs in + Printf.printf "A: %06X\n" regs.a; + Printf.printf "B: %06X\n" regs.b; + Printf.printf "X: %06X\n" regs.x; + Printf.printf "L: %06X\n" regs.l; + Printf.printf "S: %06X\n" regs.s; + Printf.printf "T: %06X\n" regs.t; + Printf.printf "PC: %06X\n" regs.pc; + Printf.printf "SW: %06X\n" regs.sw; + Printf.printf "\n" \ No newline at end of file diff --git a/ass2/SICocaml/test.ml b/ass2/SICocaml/test.ml new file mode 100644 index 0000000..bec4bd9 --- /dev/null +++ b/ass2/SICocaml/test.ml @@ -0,0 +1,43 @@ +(* test_execute.ml *) + +open Processor (* assuming your state, regs, and execute are defined here *) + +(* Helper to write 3-byte instruction to memory *) +let write_instruction3 state addr byte1 byte2 byte3 = + Bytes.set state.memory addr (Char.chr byte1); + Bytes.set state.memory (addr+1) (Char.chr byte2); + Bytes.set state.memory (addr+2) (Char.chr byte3) + +(* Test function *) +let test_execute () = + (* Create a dummy state *) + let mem_size = 1024 in + let memory = Bytes.make mem_size '\000' in + let regs = { + a = 4; b = 0; x = 0; l = 0; s = 0; t = 0; f = 0.0; + pc = 0; sw = 0 + } in + let state = { memory; regs } in + + (* Example: Write a LDA instruction at address 0*) + Processor.write_instruction3 state 0 '\x01' '\x00' '\x23'; + + (* Write the operand value at 0x010 *) + Processor.writeMemAddr state 0x010 0x123456; + + (* Set PC to 0 *) + state.regs.pc <- 0; + + Printf.printf "Before execution:\n"; + Processor.print_regs state; + Processor.print_memory state 15; + + (* Execute instruction *) + Izvajalnik.execute state; + + Printf.printf "After execution:\n"; + Processor.print_regs state; + Processor.print_memory state 15 + +(* Run the test *) +let () = test_execute ()