added instruction functionality
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zanostro
parent
483a16c194
commit
d4754a048d
9 changed files with 754 additions and 170 deletions
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@ -4,6 +4,7 @@
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#include "opcode.h"
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#include "instructions.h"
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#include <cmath>
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using std::make_shared;
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@ -128,23 +129,93 @@ void Machine::setWord(int address, int value)
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cerr << prefix << "Invalid memory address: " << address << endl;
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return;
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}
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value &= 0xFFFFFF;
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memory[address] = static_cast<unsigned char>(value & 0xFF);
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memory[address + 1] = static_cast<unsigned char>((value >> 8) & 0xFF);
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memory[address + 2] = static_cast<unsigned char>((value >> 16) & 0xFF);
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}
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// TODO: implement proper float storage and retrieval
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double Machine::getFloat(int address)
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{
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return 0.0;
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if (address < 0 || address + 5 >= MEMORY_SIZE) {
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cerr << prefix << "Invalid float address: " << address << endl;
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return 0.0;
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}
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// load 6 bytes, little-endian → 48-bit word
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unsigned long long raw =
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(unsigned long long)memory[address] |
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((unsigned long long)memory[address+1] << 8) |
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((unsigned long long)memory[address+2] << 16) |
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((unsigned long long)memory[address+3] << 24) |
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((unsigned long long)memory[address+4] << 32) |
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((unsigned long long)memory[address+5] << 40);
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int sign = (raw >> 47) & 0x1;
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int exponent = (raw >> 40) & 0x7F;
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unsigned long long frac = raw & SICF_FRAC_MASK; // 40 bits
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if (raw == 0) return 0.0;
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// value = (1 + frac/2^40) * 2^(exp - 64)
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double mant = 1.0 + (double)frac / (double)(1ULL << SICF_FRAC_BITS);
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int e = exponent - SICF_EXP_BIAS;
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double val = std::ldexp(mant, e); // ldexp is fast enough here
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return sign ? -val : val;
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}
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void Machine::setFloat(int address, double value)
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{
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// TODO: implement proper float storage
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if (address < 0 || address + 5 >= MEMORY_SIZE) {
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cerr << prefix << "Invalid float address: " << address << endl;
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return;
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}
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if (value == 0.0) {
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memory[address] = 0;
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memory[address+1] = 0;
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memory[address+2] = 0;
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memory[address+3] = 0;
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memory[address+4] = 0;
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memory[address+5] = 0;
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return;
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}
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int sign = value < 0;
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double x = sign ? -value : value;
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// normalize x to [1, 2)
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int exp2 = 0;
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x = std::frexp(x, &exp2);
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x *= 2.0;
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exp2 -= 1;
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int exp_field = exp2 + SICF_EXP_BIAS;
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if (exp_field < 0) exp_field = 0;
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if (exp_field > 127) exp_field = 127;
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// mantissa = (x - 1) * 2^40
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double frac_d = (x - 1.0) * (double)(1ULL << SICF_FRAC_BITS);
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unsigned long long frac = (unsigned long long)(frac_d + 0.5); // round
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frac &= SICF_FRAC_MASK;
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unsigned long long raw =
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((unsigned long long)sign << 47) |
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((unsigned long long)exp_field << 40) |
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frac;
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// store 6 bytes little-endian
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memory[address] = (unsigned char)( raw & 0xFF);
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memory[address+1] = (unsigned char)((raw >> 8) & 0xFF);
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memory[address+2] = (unsigned char)((raw >> 16) & 0xFF);
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memory[address+3] = (unsigned char)((raw >> 24) & 0xFF);
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memory[address+4] = (unsigned char)((raw >> 32) & 0xFF);
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memory[address+5] = (unsigned char)((raw >> 40) & 0xFF);
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}
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Device &Machine::getDevice(int num)
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{
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if(num < 0 || num >= static_cast<int>(devices.size()) || !devices[num]) {
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@ -195,49 +266,48 @@ int Machine::fetch()
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return getByte(PC++);
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}
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void Machine::execute()
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{
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int opcode = fetch();
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InstructionType type = instructions[opcode].type;
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switch (type) {
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case InstructionType::TYPE1: execF1(opcode);break;
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case InstructionType::TYPE2: execF2(opcode, fetch());break;
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case InstructionType::TYPE3_4: // extract n and i bits
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{
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int ni = opcode & 0x3;
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int operand = fetch();
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execSICF3F4(opcode, ni, operand);
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}
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break;
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default: invalidOpcode(opcode); break;
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void Machine::execute() {
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int b1 = fetch();
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InstructionInfo &info = instructions[b1];
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if (info.type == InstructionType::TYPE1) { execF1(b1); return; }
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if (info.type == InstructionType::TYPE2) { execF2(b1, fetch()); return; }
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int opcode = b1 & TYPE3_4_SIC_MASK;
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InstructionInfo &info34 = instructions[opcode];
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int ni = b1 & NI_MASK;
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if (info34.type == InstructionType::TYPE3_4) {
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int b2 = fetch(), b3 = fetch();
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int x = (b2 & 0x80) ? 1 : 0;
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int b = (b2 & 0x40) ? 1 : 0;
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int p = (b2 & 0x20) ? 1 : 0;
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int e = (b2 & 0x10) ? 1 : 0;
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int operand;
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if (ni == NI_SIC) {
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// PURE SIC
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operand = ((b2 & 0x7F) << 8) | b3;
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} else {
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// SIC/XE
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operand = e
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? (((b2 & 0x0F) << 16) | (b3 << 8) | fetch()) // F4: 20-bit
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: (((b2 & 0x0F) << 8) | b3); // F3: 12-bit
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}
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execSICF3F4(opcode, ni, x, b, p, e, operand);
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return;
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}
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invalidOpcode(b1);
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}
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bool Machine::execF1(int opcode)
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{
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switch (opcode)
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{
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case FIX:
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setA(static_cast<int>(getF()));
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return true;
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case FLOAT:
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setF(static_cast<double>(getA()));
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return true;
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case HIO:
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notImplemented("HIO");
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return true;
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case NORM:
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notImplemented("NORM");
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return true;
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case SIO:
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notImplemented("SIO");
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return true;
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case TIO:
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notImplemented("TIO");
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return true;
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default:
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break;
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}
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undefinedHandler(opcode);
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return false;
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}
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@ -255,7 +325,47 @@ bool Machine::execF2(int opcode, int operand)
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return false;
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}
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bool Machine::execSICF3F4(int opcode, int ni, int operand)
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bool Machine::execSICF3F4(int opcode, int ni, int x, int b, int p, int e, int operand)
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{
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int ea_part = operand;
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int base = 0;
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AddressingMode mode = getAddressingMode(ni);
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// --- PURE SIC ---
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if (mode == AddressingMode::SIC_DIRECT) {
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int ea = ea_part + (x ? getX() : 0);
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if (instructions[opcode].handler) {
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auto h = reinterpret_cast<void(*)(Machine&, int, AddressingMode)>(instructions[opcode].handler);
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h(*this, ea, mode);
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return true;
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}
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undefinedHandler(opcode);
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return false;
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}
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// --- SIC/XE EA calc ---
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if (!e) { // format 3
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if (b && !p) {
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base = getB(); // base-relative, unsigned 12-bit
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} else if (p && !b) {
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// PC-relative, signed 12-bit
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if (ea_part & 0x800) // bit 11 set?
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ea_part |= 0xFFFFF000; // sign-extend
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base = getPC();
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}
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}
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// format 4 (e=1): b/p ignored, ea_part is 20-bit absolute
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int ea = base + ea_part + (x ? getX() : 0);
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if (instructions[opcode].handler) {
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auto h = reinterpret_cast<void(*)(Machine&, int, AddressingMode)>(instructions[opcode].handler);
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h(*this, ea, mode);
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return true;
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}
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undefinedHandler(opcode);
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return false;
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}
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