zs7976/spo
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

added extra istructions

Browse source
This commit is contained in:
zanostro 2025-11-16 02:10:14 +01:00
parent ad3078ba48
commit ba18b92116
8 changed files with 470 additions and 123 deletions
Download patch file Download diff file Expand all files Collapse all files

34
simulator_SIC_XE/include/machine.h
View file

@ -26,7 +26,7 @@ using std::cout;
class Machine {
public:
Machine();
Machine(int speedkHz) : Machine() { this->speedkHz = speedkHz; }
Machine(int speedkHz) : Machine() { this->speedkHz = speedkHz; _instructionsTable = instructions; }
~Machine();
int getA() const { return A; }
@ -82,16 +82,13 @@ public:
int fetch();
void execute();
bool execF1(int opcode);
bool execF2(int opcode, int operand);
bool execSICF3F4(int opcode, int ni, int x, int b, int p, int e, int operand);
// Execution and speed control
int getSpeed() const;
void setSpeed(int kHz);
void start();
void stop();
void tick();
void halt();
// error handling methods
void notImplemented(string mnemonic);
@ -100,6 +97,22 @@ public:
void divisionByZero(int opcode);
void undefinedHandler(int opcode);
bool getExtendedMode() const { return _exex_mode; }
void enableExtendedMode();
void disableExtendedMode();
int* getVectorRegister(int regNum);
void setVectorRegister(int regNum, const int* values);
const int* getVA() const { return VA; }
const int* getVS() const { return VS; }
const int* getVT() const { return VT; }
void setVA(const int* values);
void setVS(const int* values);
void setVT(const int* values);
private:
// registers
int A, B, X, L, S, T, PC, SW;
@ -116,6 +129,17 @@ private:
// Execution control
std::atomic<bool> running{false};
std::atomic<int> speedkHz{1}; // Default 1 kHz
bool execF1(int opcode);
bool execF2(int opcode, int operand);
bool execSICF3F4(int opcode, int ni, int x, int b, int p, int e, int operand);
// Extended mode
bool _stopped{false};
bool _exex_mode{false};
InstructionInfo* _instructionsTable;
int VA[VECTOR_REG_SIZE], VS[VECTOR_REG_SIZE], VT[VECTOR_REG_SIZE]; // vector operation registers
};