added extra istructions

simulator_SIC_XE/include/constants.h

@@ -35,4 +35,9 @@ constexpr int BP_DIRECT_MASK = 0b00;
 
 constexpr int BIT_E_MASK = 0x10; // mask for e bit in F4 and F3 instructions
 
+//SIC/XE/XE
+constexpr bool USE_EXTENDED_MODE = true;
+constexpr int VECTOR_REG_SIZE = 4;
+
+
 #endif // CONSTANTS_H

simulator_SIC_XE/include/instructions.h

@@ -12,6 +12,7 @@ void hio_handler(Machine& m);
 void norm_handler(Machine& m);
 void sio_handler(Machine& m);
 void tio_handler(Machine& m);
+void nop_handler(Machine& m);
 
 /* IDEJE ZA SIC_XE_XE :)*/
 // void nop(Machine& m);
@@ -75,4 +76,26 @@ void tix_handler(Machine& m, int ea, AddressingMode mode);
 void wd_handler(Machine& m, int ea, AddressingMode mode);
 
 
+// SIC/XE/XE Extended instruction handlers
+void xexe_handler(Machine& m);
+void halt_handler(Machine& m);
+void nop_handler(Machine& m);
+
+void vaddr_handler(Machine& m, int r1, int r2);
+void vsubr_handler(Machine& m, int r1, int r2);
+void vmulr_handler(Machine& m, int r1, int r2);
+void vdivr_handler(Machine& m, int r1, int r2);
+
+void vadd_handler(Machine& m, int ea, AddressingMode mode);
+void vsub_handler(Machine& m, int ea, AddressingMode mode);
+void vmul_handler(Machine& m, int ea, AddressingMode mode);
+void vdiv_handler(Machine& m, int ea, AddressingMode mode);
+void stva_handler(Machine& m, int ea, AddressingMode mode);
+void stvs_handler(Machine& m, int ea, AddressingMode mode);
+void stvt_handler(Machine& m, int ea, AddressingMode mode);
+void ldva_handler(Machine& m, int ea, AddressingMode mode);
+void ldvs_handler(Machine& m, int ea, AddressingMode mode);
+void ldvt_handler(Machine& m, int ea, AddressingMode mode);
+
+
 #endif // INSTRUCTIONS_H

simulator_SIC_XE/include/machine.h

@@ -26,7 +26,7 @@ using std::cout;
 class Machine {
 public:
     Machine();
-    Machine(int speedkHz) : Machine() { this->speedkHz = speedkHz; }
+    Machine(int speedkHz) : Machine() { this->speedkHz = speedkHz; _instructionsTable = instructions; }
     ~Machine();
 
     int getA() const { return A; }
@@ -82,16 +82,13 @@ public:
     int fetch();
     void execute();
 
-    bool execF1(int opcode);
-    bool execF2(int opcode, int operand);
-    bool execSICF3F4(int opcode, int ni, int x, int b, int p, int e, int operand);
-
     // Execution and speed control
     int getSpeed() const;
     void setSpeed(int kHz);
     void start();
     void stop();
     void tick();
+    void halt();
 
     // error handling methods
     void notImplemented(string mnemonic);
@@ -100,6 +97,22 @@ public:
     void divisionByZero(int opcode);
     void undefinedHandler(int opcode);
 
+    bool getExtendedMode() const { return _exex_mode; }
+    void enableExtendedMode();
+    void disableExtendedMode();
+
+
+    int* getVectorRegister(int regNum);
+    void setVectorRegister(int regNum, const int* values);
+
+    const int* getVA() const { return VA; }
+    const int* getVS() const { return VS; }
+    const int* getVT() const { return VT; }
+    void setVA(const int* values);
+    void setVS(const int* values);
+    void setVT(const int* values);
+
+
 private:
     // registers
     int A, B, X, L, S, T, PC, SW;
@@ -116,6 +129,17 @@ private:
     // Execution control
     std::atomic<bool> running{false};
     std::atomic<int> speedkHz{1};  // Default 1 kHz
+
+    bool execF1(int opcode);
+    bool execF2(int opcode, int operand);
+    bool execSICF3F4(int opcode, int ni, int x, int b, int p, int e, int operand);
+
+
+    // Extended mode
+    bool _stopped{false};
+    bool _exex_mode{false};
+    InstructionInfo* _instructionsTable;
+    int VA[VECTOR_REG_SIZE], VS[VECTOR_REG_SIZE], VT[VECTOR_REG_SIZE]; // vector operation registers
 };
 
 

simulator_SIC_XE/include/opcode.h

@@ -66,6 +66,28 @@
 #define TIXR    0xB8
 #define WD      0xDC
 
+// ==============================
+// Extended opcodes (SIC/XE/XE)
+// ==============================
+#define NOP     0xF1
+#define HALT    0xF2
+#define XEXE    0xEE // Enable extended mode
+#define VADD    0x18
+#define VADDR   0x90
+#define VSUB    0x1C
+#define VSUBR   0x94
+#define VMUL    0x20
+#define VMULR   0x98
+#define VDIV    0x24
+#define VDIVR   0x9C
+#define STVA    0x0C
+#define STVS    0x7C
+#define STVT    0x84
+#define LDVA    0x00
+#define LDVS    0x68
+#define LDVT    0x04
+
+
 
 enum class InstructionType {
     TYPE1,
@@ -86,6 +108,7 @@ struct InstructionInfo {
 };
 
 extern InstructionInfo instructions[];
+extern InstructionInfo instructionsEXEX[];
 
 // Initialize the instruction table
 void loadInstructionSet();