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Timon 2025-11-10 13:41:50 +01:00
parent d9b2e0432e
commit 9ef89d8772
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.gitignore vendored
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#Ignorej zacetni primer #Ignorej zacetni primer
Primer/ Primer/
#Ignorej sictools #Ignorej sictools
sictools.jar sictools.jar
#ignorej ukaze za sic/xe
Appendix_A_thru_C.pdf

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ass1/Rekurzija/FA.dev Normal file
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ass1/Rekurzija/rek.asm Normal file
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rek START 0
loop RD #0xFA
COMP #1
JLT halt
JSUB fa
WD #1
CLEAR A
J loop
halt J halt
fa STL @stkp
JSUB spush
STB @stkp
JSUB spush
. Base case
COMP #2
JLT faExit
RMO A, B
SUB #1
JSUB fa
MULR B, A
faExit JSUB spop
LDB @stkp
JSUB spop
LDL @stkp
RSUB
sinit STA stkA
LDA #stk
STA stkp
LDA stkA
RSUB
spush . stkp++
STA stkA
LDA stkp
ADD #3
STA stkp
LDA stkA
RSUB
spop . stkp--
STA stkA
LDA stkp
SUB #3
STA stkp
LDA stkA
RSUB
stkp WORD 0
stk RESW 1000
stkA WORD 0
END rek