working...

ass2/SICocaml/izvajalnikF2.ml

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+(*r2 <- (r2) + (r1)*)
+let addr (state : Processor.state) (r1 : int) (r2 : int) : unit = 
+  let valR1 = Processor.read_register_int state r1 in
+  let valR2 = Processor.read_register_int state r2 in
+  Processor.write_register_int state r2 (valR1 + valR2)
+
+(*r1 <- 0*)
+let clear (state : Processor.state) (r1 : int) : unit = 
+  Processor.write_register_int state r1 0
+
+  (*(r1):(r2)*)
+let compr (state : Processor.state) (r1 : int) (r2 : int) : unit = 
+  let sw = 9 in
+  let valR1 = Processor.read_register_int state r1 in
+  let valR2 = Processor.read_register_int state r2 in
+    Processor.write_register_int state sw (if valR1 < valR2 then 0 else if valR1 = valR2 then 1 else 2)
+
+(*r2 <- (r2) / (r1)*)
+let divr (state : Processor.state) (r1 : int) (r2 : int) : unit = 
+  let valR1 = Processor.read_register_int state r1 in
+  let valR2 = Processor.read_register_int state r2 in
+  Processor.write_register_int state r2 (valR2 / valR1)
+
+(*r2 <- (r2) * (r1)*)
+let mulr (state : Processor.state) (r1 : int) (r2 : int) : unit = 
+  let valR1 = Processor.read_register_int state r1 in
+  let valR2 = Processor.read_register_int state r2 in
+  Processor.write_register_int state r2 (valR2 * valR1)
+
+(*r2 <- (r1)*)
+let rmo (state : Processor.state) (r1 : int) (r2 : int) : unit = 
+  let valR1 = Processor.read_register_int state r1 in
+  Processor.write_register_int state r2 (valR1)
+
+(*r1 <- (r1); left shift n bits. {In assembled instruction, r2 = n-1}*)
+let shiftl(state : Processor.state) (r1 : int) (r2 : int) = 
+  let n = r2 + 1 in
+  let valR1 = Processor.read_register_int state r1 in
+  Processor.write_register_int state r1 (valR1 lsl n)
+
+(*r1 <- (r1); right shift logical n bits. {In assembled instruction, r2 = n-1}*)
+let shiftr(state : Processor.state) (r1 : int) (r2 : int) = 
+  let n = r2 + 1 in
+  let valR1 = Processor.read_register_int state r1 in
+  Processor.write_register_int state r1 (valR1 lsr n)
+
+(*r2 <- (r2) - (r1)*)
+let subr (state : Processor.state) (r1 : int) (r2 : int) : unit = 
+  let valR1 = Processor.read_register_int state r1 in
+  let valR2 = Processor.read_register_int state r2 in
+  Processor.write_register_int state r2 (valR2 - valR1)
+
+(*X <- (X) + 1; (X):(r1)*)
+let tixr (state : Processor.state) (r1 : int) : unit = 
+  state.regs.x <- state.regs.x + 1;
+  let sw = 9 in
+  let valR1 = Processor.read_register_int state r1 in
+  let valX = state.regs.x in
+  Processor.write_register_int state sw (if valX < valR1 then 0 else if valX = valR1 then 1 else 2)