ab76015/spo
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

checkpoint, execf1, execf2 done

Browse source
This commit is contained in:
aljazbrodar. 2025-12-06 10:57:07 +01:00
parent 5c6d1b22f6
commit e65262a3e0
272 changed files with 193 additions and 38 deletions
Download patch file Download diff file Expand all files Collapse all files

113
ass2/simulator/machine.cpp
View file

@ -29,7 +29,6 @@ int Machine::getReg(int reg)
case 3: return B;
case 4: return S;
case 5: return T;
case 6: return F;
case 8: return PC;
case 9: return SW;
default: return -1;
@ -95,8 +94,8 @@ void Machine::setDevice(int num, Device* device) {
}
void Machine::notImplemented(string mnemonic) {
std::cerr << "Instruction: " << mnemonic << " is not yet implemented." << endl;
void Machine::notImplemented(int opcode) {
std::cerr << "Instruction: " << opcode << " is not yet implemented." << endl;
}
void Machine::invalidOpcode(int opcode) {
@ -115,35 +114,99 @@ int Machine::fetch() {
return readByte(address);
}
bool Machine::execF1(int opcode){
switch (opcode) {
case Opcode::FIX:
setA(static_cast<int>(getF()));
return true;
case Opcode::FLOAT:
setF(static_cast<double>(getA()));
return true;
default:
notImplemented(opcode);
break;
}
return false;
}
bool Machine::execF2(int opcode, int operand) {
int r1 = (operand >> 4) & 0xF;
int r2 = operand & 0xF;
int n;
switch (opcode) {
case Opcode::ADDR:
setReg(r2, getReg(r2) + getReg(r1));
return true;
case Opcode::CLEAR: //v clear je le 1 reg podan in sicer v r1
setReg(r1, 0);
return true;
case Opcode::DIVR:
setReg(r2, getReg(r2) / getReg(r1));
return true;
case Opcode::MULR:
setReg(r2, getReg(r2) * getReg(r1));
return true;
case Opcode::RMO:
setReg(r2, getReg(r1));
return true;
case Opcode::SHIFTL:
n = r2;
setReg(r1, getReg(r1) << n);
return true;
case Opcode::SHIFTR:
n = r2;
setReg(r1, getReg(r1) >> n);
return true;
case Opcode::SUBR:
setReg(r2, getReg(r2) - getReg(r1));
return true;
default:
notImplemented(opcode);
break;
}
return false;
}
bool Machine::execSICF3F4(int opcode, int ni, int operand) {
}
void Machine::execute() {
int opcode = fetch();
int operand;
switch (opcode) {
// Format 1
case Opcode::FIX:
case Opcode::FLOAT:
case Opcode::NORM:
execF1(opcode);
break;
// Format 1
case Opcode::FIX:
case Opcode::FLOAT:
case Opcode::NORM:
case Opcode::HIO:
case Opcode::TIO:
case Opcode::SIO:
execF1(opcode);
break;
// Format 2
case Opcode::ADDR:
case Opcode::CLEAR:
case Opcode::DIVR:
case Opcode::MULR:
case Opcode::RMO:
case Opcode::SHIFTL:
case Opcode::SHIFTR:
case Opcode::SUBR:
operand = fetch();
execF2(opcode, operand);
break;
// Format 2
case Opcode::ADDR:
case Opcode::CLEAR:
case Opcode::DIVR:
case Opcode::MULR:
case Opcode::RMO:
case Opcode::SHIFTL:
case Opcode::SHIFTR:
case Opcode::SUBR:
case Opcode::SVC:
operand = fetch();
execF2(opcode, operand);
break;
// Format 3/4 (SIC/XE)
default:
decode_F3_F4(opcode);
break;
// Format SIC/3/4 (SIC/XE)
default:
operand = fetch();
int ni = opcode & 0x3;
opcode = opcode & 0xFC;
execSICF3F4(opcode, ni, operand);
break;
}
}